1. Field of the Invention
The present invention relates to a differential current source circuit and more particularly to a differential current source circuit, which is a part of the structure of a digital/analog converter (DAC) of a current driving type in, for example, a color graphic system.
2. Description of the Related Art
Conventionally, an orthodox differential current source circuit used in digital to analog converters (DACs) such as a color graphics system is structured as shown in FIG. 1. This type of circuit comprises P-channel type MOSFETs P1 to P3. A current path of each of MOSFETs P1 and P2 is connected in series between a power supply V.sub.DD and a ground point (output terminal Q). A bias voltage Vref is applied to a gate of the MOSFET P1, and a digital signal .phi. is inputted to a gate of the MOSFET P2. One end of a current path of the MOSFET P3 is connected to a connecting point (node ND1) between MOSFETs P2 and P3, and the other end is connected to an output terminal Q. A digital signal .phi. (signal having an opposite phase to the digital signal .phi.) is inputted to the gate of MOSFET P3.
In the differential current source circuit, the constant current, which is generated by making the MOSFET P1 conductive by the bias voltage Vref, continues to flow to one of the output terminals Q or Q via the current path of the MOSFET P2, which is in an ON state, or the current path of the MOSFET P3. However, in the circuit structure as shown in FIG. 1, timing of digital signals .phi. and .phi. must be controlled in order to ideally transit the levels of the digital signals .phi. and .phi.. If the characteristics of MOSFETs P1 to P3 are changed due to variation during manufacturing, the voltage of the node ND1 and the output current sent from the output terminal Q will vary. Due to this, in a DAC comprising plurality of differential current source circuits connected in parallel as shown in FIG. 1, a glitch is generated by the variation of the voltage of the node ND1 of each differential current source circuit and the output current sent from the output terminal Q. In order to suitably control timing of the signals .phi. and .phi., a driver, which controls on/off switch timing of differential switches (MOSFETs P2 and P3), is needed.
As mentioned above, in the circuit structure shown in FIG. 1, since the number of additional circuits is increased so as to reduce the influence of manufacture variation upon the element characteristic, a pattern occupying area is increased. Moreover, the level change of the digital signal .phi. inputted to the gate of the MOSFET P3 is transmitted to the output terminal Q via a parasitic capacitance of the MOSFET P3. Due to this, when this type of circuit is used in a DAC, the level change in the digital signal .phi. is superimposed on the analog output voltage, which is called "field through", and deterioration of a conversion accuracy occurs.
Generally, when using a DAC of a current driving type, a load such as a resistance is connected to the output terminal Q, and the DAC is terminated by impedance. Therefore, for a DAC of the current driving type, impedance (on-resistance of transistor) of the differential switch, which is seen from the output terminal Q, is low. Due to this, as the total output current becomes larger, the quantity of output current of each differential current source circuit becomes smaller. The reduction of the output current occurs by a channel length modulation effect due to a variation (reduction in this case) of voltage VDS between the drain and source when the differential switch element is an MOS transistor. Moreover, the reduction of the output current occurs by an early effect due to the variation of the voltage VCE between the collector and emitter when the differential switch element is a bipolar transistor. Such reduction of the output current cannot be disregarded as DAC resolution becomes higher.
A differential current source circuit in which the circuit of FIG. 1 is improved is disclosed in U.S. Pat. No. 4,831,282.
As shown in FIG. 2, basically, a bias voltage in place of the digital signal .phi. is applied to the gate of the MOSFET P3 of the differential current source circuit of FIG. 1. More specifically, the circuit of FIG. 2 comprises three P-channel type MOSFETs P5 to P7. A current path of MOSFET P5 and that of MOSFET P6 are connected in series between a power source V.sub.DD and an output terminal Q. A first bias voltage Vref1 is applied to the gate of MOSFET P5, and a second bias voltage Vref2 is applied to the gate of MOSFET P6. One end of a current path of MOSFET P7 is connected to a connecting point (node ND2) between the MOSFETS P5 and P6, and the other end is connected to a ground point (output terminal Q), and a digital signal .phi. is inputted to the gate.
In such a circuit structure, since the input of the digital signal is one-phase, it is unnecessary to consider the timing of the digital signals .phi. and .phi., whose phases are opposite to each other, unlike the circuit of FIG. 1. Moreover, since a bias voltage Vref2 is applied to the gate of MOSFET P6, which is connected to the output terminal Q, the level change of the digital signal is not transmitted to the output terminal Q via the parasitic capacitance of MOSFET P6. Moreover, no field through is generated.
However, the level of each of the bias voltages Vref1 and Vref2 need to be highly stabilized. In the circuit of FIG. 2, even if the voltage of node ND2 is the lowest by ON/OFF of MOSFET P7, the output voltage varies about 1 V. Due to this, at the time of high speed switching, the bias voltages Vref1 and Vref2 are varied by the influence of the parasitic capacitance of MOSFETs P5 and P6, and the generation of glitch may be caused. In order to stabilize the bias voltages Vref1 and Vref2, it is required that a capacitor having a large capacitance be formed at the gates of MOSFETs P5 and P6. Moreover, since the gate bias of the output element (MOSFET P6) is constant, the output current of the differential current source circuit is reduced as the total of the output current increases. Furthermore, regarding setting time, which is the D/A conversion speed, since output impedance is driven by the voltage VGS (gate voltage VG=Vref2, source voltage VS=ND2) between the gate and source where "Vth+.alpha." is low, mutual conductance of MOSFET P6 is low, and the high-speed operation cannot be smoothly performed.